3D-IC Methodology Architect

Title: 3D-IC Methodology Architect

About GF
GlobalFoundries (GF) is a leading manufacturer of essential semiconductors, enabling AI at scale from the cloud to the physical world. Through deep partnerships with customers, GF delivers differentiated, power efficient and high-performance solutions for high growth markets. With global manufacturing operations across the U.S., Europe and Asia, GF is a trusted and holistic technology partner for customers around the world. GF’s talented, global team remains focused every day on security, longevity, and sustainability. For more information, visit www.gf.com.

Your Job::

The 3D-IC Methodology Architect will define and lead an integrated methodology that helps customers and internal product teams move from system architecture and chiplet planning through package co-design, multi-die implementation, multi-physics sign-off and foundry tapeout. The role combines hands-on technical depth with cross-functional leadership across design enablement, PDK and IP teams, packaging, product lines, manufacturing, OSATs and EDA partners.

The successful candidate will establish reusable reference vehicles, qualified multi-vendor flows, automation and training assets that improve design predictability, reduce late-stage rework and scale 3D-IC adoption across digital, memory, RF, silicon photonics, power and mixed-technology applications.

What You Will Deliver

• Reusable system-level reference examples, beginning with digital-on-digital and digital-on-memory and expanding to digital-on-IVR, RF plus digital, photonics plus CMOS and advanced stacked systems.

• Package and system co-design methods for package trade studies, die-to-die planning and system-technology co-optimization.

• Production-ready multi-die physical implementation flows covering floorplanning, interposer and RDL implementation, assembly definition and verification.

• Qualified thermal, IR-drop, power-integrity and EMIR sign-off methods, progressing toward comprehensive multi-physics reliability sign-off.

• 3D-IC PDK, reference IP, EDA-flow and automation readiness across priority technology platforms.

• Manufacturing ready tapeout workflows across package technologies and integration options, with clear data requirements, checks and handoffs.

• A sustainable methodology ownership model, knowledge repository and training curriculum for internal teams and customers.

Essential Responsibilities:

• Own the 3D-IC methodology roadmap and translate business, product-line and customer requirements into prioritized design-flow capabilities, technical specifications and measurable qualification plans.

• Architect end-to-end workflows spanning system planning, chiplet partitioning, package selection, die-to-die connectivity, implementation, verification, sign-off and tapeout.

• Develop and validate reference vehicles that demonstrate foundry, EDA, IP and packaging capabilities and can be reused for customer demonstrations, training and flow qualification.

• Lead package trade studies and establish STCO methods that connect architecture choices with process, package, power, performance, thermal, mechanical, cost and manufacturability constraints.

• Define multi-die implementation methods for floorplanning, bump and interface planning, interposer/RDL routing, power delivery, assembly integration and physical verification.

• Build electro-thermal and EMIR methodology for early hotspot and IR-drop detection and for sign-off correlation across chiplet, package and system boundaries.

• Partner with internal process/PDK, IP, substrate, packaging, manufacturing and product-line teams to define 3D-IC design-kit content and release criteria.

• Engage EDA vendors to close tool and interoperability gaps, qualify multi-vendor flows and influence product roadmaps. Relevant ecosystems may include Cadence Integrity 3D-IC, Allegro X, Innovus, Voltus and Celsius; Synopsys 3DIC Compiler, Fusion Compiler, RedHawk-SC, PrimePower and PrimeSim; Siemens Innovator3D IC, Xpedition, Aprisa, Calibre 3DSTACK and mPower; and Ansys Icepak and chip-package-system analysis solutions.

• Standardize tapeout data, assembly instructions, verification checks and cross-organizational handoffs to improve first-pass predictability and customer execution confidence.

• Lead cross-geo technical teams, scope work packages, review technical quality, resolve ambiguity and communicate status, risks and decisions to engineering and business stakeholders.

• Mentor engineers, establish reusable automation and regression practices, and deliver methodology documentation and training for internal users and customers.

Required Qualifications

• Bachelor's, Master's or PhD degree in Electrical Engineering, Computer Engineering or a closely related discipline.

• Typically 15+ years of semiconductor design, design enablement, EDA methodology or related industry experience, including 10+ years in advanced design flows, IP enablement or methodology development.

• Demonstrated technical leadership of complex, cross-functional methodology programs involving internal teams, customers and external ecosystem partners.

• Deep knowledge of at least three of the following: 3D-IC or chiplet architecture, advanced packaging, multi-die physical implementation, die-to-die interfaces, thermal analysis, EMIR/power integrity, EMAG, physical verification or foundry tapeout.

• Working expertise with industry-standard analog, RF, AMS and/or digital implementation and verification tools, plus the ability to define integration-level requirements across domains.

• Experience defining qualification criteria, creating reference designs, correlating analysis with implementation/sign-off results and deploying repeatable flows.

• Proficiency in Linux/Unix environments and practical experience with scripting, version control, configuration management and regression infrastructure.

• Excellent written and verbal English communication, technical problem-solving and stakeholder-management skills.

Preferred Qualifications

• Hands-on experience with heterogeneous integration applications such as digital-on-memory, digital-on-IVR, RF plus digital, silicon photonics plus CMOS, wafer-to-wafer or die-to-wafer integration.

• Experience with 2.5D/3D package technologies, interposers, RDL, hybrid bonding, OSAT interfaces or substrate design and verification.

• Understanding of reliability concerns including self-heating, thermal-mechanical stress, warpage, bonding integrity and cracking risk.

• Programming and automation experience in Python, Tcl, Perl, Java or comparable languages; interest in applying generative AI to methodology productivity is beneficial.

• Experience developing customer-facing documentation, workshops, demonstrations or training for advanced design flows.

• Program or project-management skills, including milestone planning, dependency management, risk tracking and execution across ambiguous problem spaces.

Measures of Success

• Validated reference vehicles and a customer-demonstration platform are operational.

• Priority 3D-IC design kits, reference IP and partner-qualified EDA flows are released and reusable.

• Package, implementation and sign-off analyses identify risks early and minimize rework between planning, implementation and tapeout.

• Production workflows support multiple package technologies and provide clear, repeatable tapeout execution.

• A cross-functional 3D-IC methodology ownership model, knowledge repository and training curriculum are established and actively used.

Leadership & Collaboration Expectations

This is a senior individual-contributor and technical-leadership role. The architect is expected to create alignment across organizations without relying solely on direct authority, make technically sound trade-offs, communicate decisions clearly, and develop the next generation of methodology talent.

Environmental, Health, Safety & Security

Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety and Security requirements and programs.

Candidate fit: This role is best suited to a systems-minded methodology leader who can connect semiconductor process, chiplets, packaging, EDA and manufacturing into a qualified, scalable architecture-to-tapeout platform.

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